The present invention relates to a power semiconductor device used under a current with a large current density and particularly to a MOS semiconductor device such as a trench type insulated gate bipolar transistor (hereinafter abbreviated as an IGBT). Specifically, the invention relates to a trench type insulated gate MOS semiconductor device having a plurality of straight-line-like trenches formed on a top surface of a semiconductor substrate, a gate insulator film formed on the inside surface of each of the trenches, and a control electrode buried in each of the trenches with the gate insulator film interposed between to form a trench MOS gate pattern with a plurality of regions on the surfaces of the semiconductor substrate each with first conductivity type regions and second conductivity type regions alternately arranged in the longitudinal direction of the trench between the adjacent ones of a plurality of the straight-line-like trenches.
In compliance with recent requirements for downsizing and performance enhancement in power source equipment in the field of power electronics, efforts have been concentrated on improving performance parameters of a power semiconductor device such as a high breakdown voltage, a high current capacity and along with this, a low power loss, a high breakdown blocking capability and a high operation speed. For a power semiconductor device capable of obtaining such a high current capacity and a low power loss, vertical and trench gate type IGBTs are preferably used in recent years.
A vertical and trench gate type IGBT is driven by a MOS (Metal/Oxide film/Semiconductor) gate. About the structure of the MOS gate, two types are generally well known, i.e. a planar MOS gate structure and a trench gate structure. The planar MOS gate structure has a MOS gate provided in plane-like on the surface of a semiconductor substrate, in which structure a channel current flows in the direction parallel to the surface. While, the trench gate structure has a MOS gate buried in a trench, in which structure a channel current flows in the direction perpendicular to the surface of a semiconductor substrate. Recently, a trench gate type IGBT having a gate electrode buried in a trench has been becoming a focus of attention because the structure thereof can enhance a channel density and provides easiness in obtaining low on-resistance characteristics.
Furthermore, there are two types of structures in the vertical and trench gate type IGBT having such a trench gate structure. FIG. 14 is a cross sectional view showing one of the structures (the structure is provided as that of an example 1 of a related device). As disclosed in the cross sectional view in FIG. 14, the structure of example 1 of a related device has an arrangement in which surface regions 16 and 17 between trenches 13 and a floating p region 12b as a surface region between the trenches 13 are alternately arranged. The trenches 13 are capable of performing a MOS gate function and n+ type emitter regions 16 and p+ type body regions 17 allow an emitter electrode 19 to be in contact thereto. The floating p region 12b is a region to which the emitter electrode 19 is in contact with an insulator film 18 interposed between. The alternate arrangement, when the whole active section (a region in which a main current flows) is viewed from above, can be said as an arrangement that is referred to as being a so-called stripe patterned one. In the floating p region 12b, holes, being hardly emitted to the emitter electrode 19, tend to accumulate in the floating p region 12b to make the carrier concentration distribution in a drift layer 11 of an n-type come close to that in a diode. The floating p region 12b, as explained before, is covered with the insulator film 18 without being provided with the trench gate structure section. This reduces the capacitance between a gate electrode 15 and the emitter electrode 19 by the capacitance of the trench gate structure section to shorten a time for charging or discharging the capacitance of the floating p region 12b, which provides a merit of reducing a switching loss (JP-A-2001-308327 (FIG. 1) (corresponding to U.S. Pat. No. 6,737,705 B2)). The structure is also provided as one in which, in a part of the insulator film 18 covering the surface of the floating p region 12b separated by the trenches 13 as shown in FIG. 14, an unillustrated contact hall is provided to make the emitter electrode 19 contact with the floating p region 12b in a small area to interpose resistance component in the horizontal direction of the substrate in the floating p region 12b between the emitter electrode 19 and the drift layer 11, which provides a merit similar to that as described before (JP-A-2001-308327 (FIG. 1) (corresponding to U.S. Pat. No. 6,737,705 B2) and JP-A-2004-39838).
FIG. 15 is a perspective cross sectional view showing the other structure (the structure is referred to as that of an example 2 of a related device). The structure of example 2 of a related device, as shown in FIG. 15, has an arrangement in which a plurality of trenches 13, each being filled with a gate electrode 15 with a gate insulator film 14 interposed between, are arranged in a surface pattern of a plurality of straight lines and p base regions 12 and regions of an n-type semiconductor substrate as the n-type drift layer 11 are alternately arranged on each surface of the n-type semiconductor substrate as the n-type drift layer 11 between trenches 13 in the longitudinal direction along the trenches 13. In other words, the structure, when the whole active section is viewed from above, can be said as one in which the rows of the p base regions 12 and the rows of the regions of the n-type semiconductor substrate as the n-type drift layer 11 alternately intersect perpendicularly to the parallel trenches 13. In the structure, although the structure is provided as a trench gate structure, a channel current comes to flow not only in the direction perpendicular to the surface of the n-type semiconductor substrate 11 but also in the direction parallel to the n-type semiconductor substrate 11. This makes the vertical and trench gate type IGBT to enable realization of low on-resistance and a high breakdown voltage at the same time (JP-A-2000-228519 (FIG. 6 and FIG. 7) (corresponding to U.S. Pat. No. 6,380,586 B2 and Publication of German Patent Application DE 10 004 548 A)). Moreover, a structure is also presented in which a p base region is surrounded by an n+-type region with an impurity concentration (density) higher than that in the semiconductor substrate to thereby increase a hole concentration (density) near the surface of an n base layer (drift layer) (JP-A-8-316479 (corresponding to U.S. Pat. No. 6,221,721 B2)).
Furthermore, a method is known in which a tradeoff characteristic is improved by thinning a drift layer rather than carrying out the method from the view point of increasing a carrier concentration (density) on the surface side of a drift layer as explained before. For example, there is a punch-through type device in which a thin epitaxial layer with the lowest possible impurity concentration (density) is formed for making the device provided with an n base layer (drift layer) thinned while keeping a specified breakdown voltage. The thinned epitaxial layer is formed on a semiconductor substrate with a high impurity concentration (density) together with a buffer layer with a high impurity concentration (density) to keep the breakdown voltage of the device. Furthermore, there are devices such as a field stop type device in which, between a p-type collector layer, formed on the other principal surface of a semiconductor substrate with the impurity concentration being controlled, and a drift layer formed of the semiconductor substrate, a field stop layer (or a buffer layer) is provided with its thickness and its impurity concentration (density) being controlled.
About the structure and operation of a related vertical and trench type IGBT of an example 2 as described in JP-A-2000-228519 (FIG. 6 and FIG. 7) (corresponding to U.S. Pat. No. 6,380,586 B2 and Publication of German Patent Application DE 10 004 548 A), an explanation will be made with reference to FIG. 15, FIG. 16-1 to FIG. 16-3. FIG. 16-1 to FIG. 16-3 are cross sectional views taken on a cross section A, a cross section B and a cross section C, respectively, shown in FIG. 15. In the following explanations, a “trench type IGBT” is to be referred to as an IGBT having a structure in which a channel current flows in both of the directions perpendicular to and parallel to the substrate as explained before. In the related IGBT of example 2, on one of the principal surfaces (hereinafter referred to as the top surface) of a semiconductor substrate (n−-type drain layer) 11, a p base region 12 is selectively formed and, on the other principal surface (hereinafter referred to as the bottom surface), an n-type FS (field stop) layer 50, a p-type collector layer 51 and a collector electrode 22 are formed. Moreover, a number of trenches 13 are formed from the top surface of the substrate to a depth reaching the n−-type drain layer 11 over the depth of the p base region 12. On the inner surface of each of the trenches 13, a gate insulator film 14 is formed. On the further inside of the trench 13, a gate electrode 15 of a material such as conductive polycrystalline silicon is buried. On the surface of the p base region 12, a p+-type body region 17 is provided at the approximate midpoint between the trenches 13 adjacent to each other. Adjacent to each of the p+-type body region 17 and the sidewall of the trench 13, an n+-type emitter region 16 is provided. On the gate electrode 15, an insulator film 18 is disposed and, on the whole surface of the active region (a region in which a main current flows) in the unit cell region of the IGBT, a metal electrode (emitter electrode) 19 of a metal such as aluminum is provided. The insulator film 18 insulates and separates the gate electrode 15 from the metal electrode 19. Moreover, openings are provided in the insulator film 18 so that the metal electrode 19 makes common ohmic contact with the surfaces of the n+-type emitter regions 16 and the p+-type body regions 17.
In the thus arranged vertical and trench type IGBT, by applying a voltage above a specified threshold value to the gate electrode 15, an n-type inversion layer (an n-channel) is formed along the sidewall of the trench 13 in the p base region 12, by which current paths are formed both in the direction perpendicular to and in the direction parallel to the substrate. This makes the vertical and trench type IGBT in a turned-on state between the emitter and the collector. By bringing the voltage applied to the gate electrode 15 to that with the specified threshold value or less, the n-type inversion layer in the p base region 12 disappears to make the vertical and trench type IGBT in a turned-off state between the emitter and the collector. With such a vertical and trench type IGBT, along the sidewall of the trench 13, current paths are formed both in the vertical direction (the vertical direction is referred to as the direction perpendicular to the surface of the semiconductor substrate as shown in FIG. 16-1) and in the lateral direction (the lateral direction is referred to as the direction parallel to the surfaces of the semiconductor substrate as shown in FIG. 16-2). Thus, compared with a related planar gate type or trench gate type IGBT, the areas of the current paths are remarkably expanded. Furthermore, between the trenches 13, minority carriers come to be accumulated in the region where the n-type semiconductor substrate layer 11 is exposed to offer the advantage of also enabling reduction in its on-resistance.
Between the applied voltage and the current density in thus arranged vertical and trench type IGBTs of related examples 1 and 2, there is a correlation, though approximate, in which a current densities are presented at present as 200 A/cm2 to 250 A/cm2 in a 600V class device, 100 A/cm2 to 150 A/cm2 in a 1200V class device and 40 A/cm2 to 60 A/cm2 in a 2500V class device, i.e. the correlation is approximately expressed as V×I≈150 kVA.
However, in the arrangement of the vertical trench type IGBT shown in before presented FIG. 15, there is a problem in that turning-off capability is low. It was found that the problem arises owing to the following cause. This will be explained by using FIG. 15, FIG. 16-1 and FIG. 16-3 again. As was explained about the background art, in the arrangement of the vertical and trench type IGBT shown in FIG. 15, two kinds of current paths are formed. The paths as one of the two are the paths of the currents (shown by arrows) flowing in the longitudinal direction (in the direction perpendicular to the principal surface of the substrate) along the sidewall of the trench of a so-called trench type IGBT as shown in FIG. 16-1, the cross sectional view taken on the cross section A in FIG. 15. The paths as the other of the two are the paths of the currents (shown by arrows) flowing in the lateral direction (in the direction parallel to the principal surface of the substrate) along the sidewall of the trench as shown in FIG. 16-2, the cross sectional view taken on the cross section B in FIG. 15. Of the two kinds of current paths, the current paths of electrons (solid line arrows) flowing in the lateral direction along the sidewall of the trench are rather similar to the electron current paths in a planar gate IGBT. However, compared with the planar gate IGBT in which hole current paths and electron current paths are in the same plane, in the arrangement of the trench type IGBT shown in FIG. 16-2, electron current paths and hole current paths are not present in the same plane. In this point, the trench type IGBT is different from the planar gate IGBT. The hole currents are to flow in the direction from the cross section B to the cross section C shown in FIG. 15. In other words, it can be said that the paths of the hole currents become current paths such that the hole currents flow in from the trench sidewall along a contact plane of an emitter electrode and a semiconductor layer. Therefore, the hole currents are to concentrate beneath the n+-type emitter region 16 to pass there. The hole current is equivalent to a base current in an NPN transistor formed with the n+-type emitter region/the p base region/the n-type semiconductor substrate layer. It was found that the concentration of the hole current makes the operation of the NPN transistor easy to result in making the operation of a parasitic thyristor of the IGBT easy which thyristor is formed with the n+-type emitter region/the p base region/the n-type semiconductor substrate/the p-type collector layer, which makes the turning-off of the IGBT uncontrollable to degrade turning-off blocking capability.
Further in the market, development of a vertical and trench type IGBT is desired which has a capacity of the order of approximately 360 kVA to 600 kVA with such a further higher breakdown voltage and a further higher current density than those of related ones as to be a high breakdown voltage of 1200V class and a current density of 300 A/cm2 to 500 A/cm2.
When the vertical and trench type IGBT as each of examples 1 and 2 of related devices is used with such a high breakdown voltage and a high current density, the arrangement shown in each of the cross sectional views of FIG. 14 (example 1 of the related device) and FIG. 15 to FIG. 16-3 (example 2 of the related device) sometimes causes avalanche breakdown to occur at turning-off of a large current with gate resistance made relatively low (such resistance causes the current to begin to reduce after a gate voltage is lowered down to a threshold voltage or less), which becomes a problem in reliability. Therefore, in many cases, the gate resistance is made relatively large (with such resistance, a gate voltage determines reduction in current). This case is to be referred to as the latter case.
The behavior of a gate voltage under the turning-off condition like in the latter case will be explained with reference to an equivalent circuit diagram showing a typical IGBT and its gate circuit, which is presented in FIG. 17. As shown in FIG. 17, the behavior of the gate voltage under the turning-off condition of an IGBT will be explained with three kinds of capacitors, a gate-collector capacitor CGC, a collector-emitter capacitor CCE and a gate-emitter capacitor CGE. In the following, the gate, the collector and the emitter will be represented by abbreviations as G, C and E, respectively. Under the turning-off condition, an increase in the collector-emitter voltage causes a displacement current (iGC) to flow through gate-collector capacitance. When a gate current ig is ig=iGC, a gate-emitter current iGE becomes iGE=0, by which a period of time appears during which no gate voltage varies (generally referred to as “Miller period”).
Under such a state, following two kinds of turning-off states can be considered.
1) The state in which the gate current ig determines iGC (i.e. ig determines dVCE/dt).
2) The state in which iGC determines ig (i.e. dVCE/dt determines ig).
Namely, when the G-C capacitance is relatively small, the state of 1) appears. Conversely, when the G-C capacitance is relatively large, the state of 2) appears. According to the inventor's investigation effort, it has been found that the turning-off under the state of 2) makes a jumping voltage smaller than the turning-off under the state of 1).
In short, about the behavior after a collector voltage reaches a bus voltage at turning-off, under the state of 1), the way of reduction in the gate voltage determines the current reduction rate of a collector current (di/dt) to determine a jumping voltage (L·di/dt). While, under the state of 2), the increasing rate of the collector voltage still continues to affect the gate current. This makes the way of reduction in the gate voltage gradual compared with the way under the state of 1). As a result, it is said that the current reduction rate (di/dt) in the collector current becomes gradual to make a spike voltage become small.
An effective layer arrangement for obtaining an effect as that under the state of 2) by a simple method is that which brings a region, being in contact with the gate electrode formed in the trench with the gate insulator film interposed between, into a floating state. With such an arrangement, however, there is a problem of causing the device to be broken at static avalanche breakdown.
In addition, when the arrangement is applied under the condition with a large current density as explained above, in the arrangement of the vertical and trench type IGBT having the floating p region as shown in FIG. 14, there is a problem in compatibility between the use at a large current density and the realization of a low on-voltage. According to the inventor's investigation effort, it has become clear that the problem is caused as follows.
This will be explained by using FIGS. 16-1 to 16-3. In general, a saturation current Isat of a MOS semiconductor device is given by the following expression (1):
                              I          sat                =                              1                          (                              1                -                                  α                  PNP                                            )                                ⁢                                                    μ                                  n                  ⁢                                                                          ⁢                  s                                            ⁢                              C                ox                            ⁢              Z                                      2              ·                              L                CH                                              ⁢                                    (                                                V                  GE                                -                                  V                                      GE                    ⁡                                          (                      th                      )                                                                                  )                        2                                              (        1        )            
where αPNP is a current-amplification factor, μns is carrier mobility in an inversion layer, COX is capacitance of a gate insulator film, Z is a total emitter width (or length), LCH is a channel length, VGE is a gate bias and VGE(th) is a threshold voltage.
For securing design freedom and for preventing other characteristics (in particular, a breakdown voltage characteristic) from being made sacrificed, the saturation current is desirably adjusted by adjusting the total emitter width (or length) Z. Here, the total emitter width (or length) Z is a width (or length) to which the widths (or lengths) of sections, at each of which the emitter region 16 in a unit cell between the trenches 13 is in contact with the trench 13, are summed about the number of the whole unit cells in a unit area. In the following, although the emitter width will be sometimes referred to as the emitter length, both are equivalent to each other.
While, as was explained in the foregoing, in the arrangement of the vertical and trench type IGBT shown in FIG. 15, two kinds of current paths are formed with the paths of the currents flowing in the direction of the thickness of the substrate in the p base region 12 along the sidewall of the trench 13 of a so-called trench type IGBT as shown in FIG. 16-1, and the paths of the currents flowing in the lateral direction parallel to the principal surface of the substrate in the p base region 12 along the sidewall of the trench as shown in FIG. 16-2. For achieving a low on-voltage, the paths of currents flowing in the lateral direction parallel to the principal surface of the substrate along the sidewall of the trench must be secured.
However, an increase only in the total emitter width (or length), performed for increasing a saturation current according to the expression (1) while maintaining the arrangement of the vertical and trench type IGBT shown in FIG. 15, inevitably causes the emitter region 16 to come close to the end of the p base region 12 in the longitudinal direction of the trench to make it impossible to form paths for allowing sufficient currents to flow in the lateral direction on the side wall of the trench. Thus, it becomes clear that such an arrangement makes it difficult to allow the IGBT to increase a current density and to lower an on-voltage.
The invention was made in view of the foregoing situation and an object of the invention is to provide a vertical and trench type insulated gate MOS semiconductor device which is capable of lowering on-resistance, increasing a current density, enhancing a breakdown blocking capability at avalanche breakdown and inhibiting a jumping voltage at turning-off.